1. Technical Field
The present invention relates to a phase locked loop (PLL) circuit having a loop filter and a method of driving the same, and more particularly, to a PLL circuit having a loop filter that generates a control voltage having a constant level and to a method of controlling the same.
2. Related Art
As the processing speed of semiconductor memory apparatuses becomes faster, the frequency of an external clock increases, and accordingly, the frequency of an internal clock also increases. When the frequency of the internal clock is increased, an operation of inputting/outputting data in synchronization with a clock becomes unstable in a semiconductor memory apparatus having a delay lock loop (DLL) circuit according to the related art. In particular, in semiconductor memory apparatuses requiring a high-speed operation, such as graphic memories, when a timing margin between data and a data strobing signal generated by the clock is reduced, the reliability of a data input operation is lowered.
Therefore, a method of providing a PLL circuit in the semiconductor memory apparatus has been introduced to improve the reliability of the data input operation. The semiconductor memory apparatus uses the PLL circuit to compare the timing of a clock with the timing of input data to determine a phase difference and control the phase of data with respect to the clock to synchronize the clock with the data, thereby improving the reliability of the data input operation.
In general, the PLL circuit includes a loop filter. There are two types of loop filters, that is, loop filters using clocks and loop filters without using a clock. The loop filters using clocks are classified into a two-stage RC filter, a self-biased loop filter, and a sample and reset filter.
The two-stage RC filter is typically used, but is sensitive to PVT (process, voltage, and temperature) characteristics, which results in a large variation in an output signal. The self-biased loop filter is insensitive to the PVT characteristics, but outputs signals with a pattern jitter. The sample and reset loop filter is not sensitive to the PVT characteristics, and is capable of removing the pattern jitter from an output signal by using an additional switch capacitor circuit.
The sample and reset loop filter requires two voltage pumps for driving a resistor and a capacitor, and the two voltage pumps require the same amount of current.
However, a difference in charge injection amount and charge distribution amount may occur between the two voltage pumps, which may cause mismatched charges between the two voltage pumps. The mismatch between the two voltage pumps may cause a variation in the level of an output voltage of the loop filter and errors in the phase fixing operation of the PLL circuit.